The CAN bus system has become widespread for communication between sensors and control units. In the CAN bus system, messages are transmitted with the aid of the CAN protocol, as described in the CAN specification in ISO 11898.
Patent document DE 10 000 305 A1 discusses the controller area network (CAN) and an enhancement of the CAN, referred to as time-triggered CAN (TTCAN). The method for controlling media access used in the CAN is based on bit-wise arbitration. In the CAN, the bit-wise arbitration is carried out based on a leading identifier within the message that is to be transmitted via the bus.
As already discussed in DE 10 2012 200 997, during bit-wise arbitration multiple user stations may simultaneously transmit data to the bus system without interfering with the data transmission.
In the CAN protocol, the bit rate in the arbitration field and the data field is the same, so that bit rate_arb=bit rate_data. The maximum bit rate is 1 megabits per second (Mbps); i.e., the bit time is 1 μs.
The CAN protocol has been developed further under the name CAN FD, according to which messages are transmitted corresponding to the specification “CAN with Flexible Data-Rate, Specification Version 1.0” (source: http://www.semiconductors.bosch.de). With CAN FD, it is possible to increase the data rate for systems in which the data rate was previously limited by the bus length of the systems.
For CAN FD, in comparison to the classical CAN, the bit rate for the subsequent data phase is increased to 2 Mbps, 4 Mbps, 8 Mbps, for example, at the end of the arbitration phase, so that bit rate_arb<bit_rate data. For the physical layer of a transceiver of a user station of a CAN FD bus system, the bit symmetry is an important parameter for error-free transmission.
During the transmission of the signals on the bus system, switching is carried out between a high signal status and a low signal status or vice versa, depending on the data to be transmitted; with regard to a transmission signal TX and a reception signal RX, the low signal status is also referred to as the dominant state, and the high signal status is also referred to as the recessive state. A signal transmitted to the bus, the bus signal, is hereby delayed with respect to transmission signal TX of a user station of the bus system. In addition, in another user station of the bus system, reception signal RX is delayed with respect to the bus signal, which results due to transmission signal TX.
Bit symmetry Bitsym may be defined as Bitsym=t_tx−t_rx, where t_tx is the bit duration at the TX input of the transceiver of the transmitting user station, and t_rx is the bit duration at the RX output of the transceiver of the same user station. The ideal bit symmetry is 0, so that t_rx=t_tx. This applies for both states, i.e., the recessive state and the dominant state.
When the bit symmetry is too low (the dominant phase is too long), communication is no longer possible, since the recessive bits ascertained at the terminal for reception signal RX are so short that the CAN protocol controller is no longer able to set a sample point. The same is true if the recessive phase is too long, as the result of which the dominant phase is too short.
The bit symmetry is independent of the bit rate. However, poor bit symmetry has a greater effect at a higher bit rate. At 500 kilobits per second (kbps), the state changes, also referred to as switching times, have much less influence on the overall bit time than at 8 Mbps, for example. At high bit rates, it is also relevant that the switching time or edge from dominant to recessive (dom=>rec) is longer than the switching time or edge from dominant to recessive (dom=>rec), since the recessive state, which is determined by the ISO standard, cannot be actively driven. A bit asymmetry thus occurs. Dominant bits become longer, and recessive bits become shorter.
The parameter of the bit symmetry has recently been introduced into the CIA CAN FD Interest Group (Spec 601-1), in which time t_rec for a recessive bit at 2 Mbps may be situated in the range of t_rec=400 . . . 550 ns, and at 5 Mbps, may be situated in the range of t_rec=120 . . . 220 ns. In this regard, line resistance RL has a value of 60 ohms, line capacitance CL has a value of 100 pF, and capacitance CRXD, which is the load capacitance present at the RXD terminal or the RXD pin, has a value of 15 pF, for example.
It is thus problematic that a lack of bit symmetry has a greater effect with increasing bit rate. If the bit symmetry required for the signal is not met, faulty transmissions in the bus system occur.